Organizer and Regional Partners
A Workshop Day will be organized on Friday, 18 September, 2015
and will take place at the Graz University of Technology, Campus Inffeldgasse.
On-site Registration: 8:00 to 18:00
Inffeldgasse 25 D
The venue can easily be reached per tram:
Get on line 6 (direction St. Peter), station Schulzentrum.
There is free parking at the Campus Inffeldgasse:
Workshop 1 (Room 1, Inffeldgasse 25d, 9:00 to 16:00)
MOS-AK: Enabling Compact Modeling R&D Exchange
Lead Organizer: Dr.-Ing. Wladek Grabinski, MOS-AK (EU)
The specific workshop goal will be to classify the most important directions for the future development of the electron device models, not limiting the discussion to compact models, but including physical, analytical and numerical models, to clearly identify areas that need further research and possible contact points between the different modeling domains. This workshop is designed for device process engineers (CMOS, SOI, BiCMOS, SiGe) who are interested in device modeling; ICs designers (RF/Analog/Mixed-Signal/SoC) and those starting in that area as well as device characterization, modeling and parameter extraction engineers. The content will be beneficial for anyone who needs to learn what is really behind the IC simulation in modern device models.
09:00 Morning MOS-AK Session
11:00 CM Standardization Panel
13:00 Afternoon MOS-AK Session
16:00 End of Workshop
Find all the PRESENTATIONS of the workshop at: http://www.mos-ak.org/graz_2015
Workshop 2 (Room 2, Inffeldgasse 25d, 8:45 to 16:00)
SINANO Workshop “New Materials for Nanoelectronic” (Full day)
Lead Presenter: Prof. Enrico Sangiorgi, University of Bologna
This Workshop is supported by the European Institute of Nanoelectronics SINANO (www.sinano.eu) and aims at discussing state-of-the-art results and disruptive achievements in the field of New Materials for Nanoelectronics. The integration of new materials (e.g. III-V compound semiconductors) on silicon platforms is foreseen as the next major evolution of advanced CMOS technology nodes. The introduction of such a disruptive innovation is a long term process where complex technological experiments must be matched by accurate Technology Computer Aided Design (TCAD) in order to reduce cost and to explore in a timely manner the available engineering options. In this workshop, leading experts in the field will report on the most recent results in fabrication, characterization and modelling of nanoelectronic devices based on new materials. Workshop highlights include a demonstration and hands-on tutorial of atomic-scale simulation that will give the audience the possibility of running examples on their own computers.
8:45 Introduction Enrico Sangiorgi, SiNANO Institute
9:00 Integration of III-V Devices on a Si Platform Nadine Collaert, IMEC
9:40 TCAD Device Simulation Frame for III-V MOS Device, Synopsy
Representatives Axel Erlebach, Fabian Bufler and Martin Frey, SYNOPSYS
10:20 III-V Heterostructures and Transition Metal Dichalcogenides for
Tunnel-FETs Marco Pala, IMEP-LAHC, Grenoble INP, NRS
11:00 Coffee Break
11:30 Graphene and Two-Dimensional (2D) Materials for Nanoelectronics
Vikram Passi, University of Siegen
12:00 Investigating the High-k/InGaAs MOSSystem for Future Logic
Applications Paul Hurley, Tyndall
13:45 Demonstration and Hands-on Tutorial of Atomic-Scale Simulation
Troels Markussen, Umberto Pozzoni, QuantumWise
16:00 Coffee Break and End of Workshop
Workshop 3 (Room 5, Inffeldgasse 25d, 8:45 to 15:30)
"Variability – From Equipment to Circuit Level" (Full day)
Lead Presenter: Dr. Jürgen Lorenz, Fraunhofer IISB
This workshop deals with process variability which is one of the key physical limitations which challenge progress in nanoelectronics. Effects from various sources of process variations, both systematic and stochastic, influence each other and lead to variations of the electrical, thermal and mechanical behavior of devices, interconnects and circuits. Correlations are of key importance because they drastically affect the percentage of products which meet the specifications. Whereas the comprehensive experimental investigation of these effects is largely impossible, modelling and simulation (TCAD) offers the unique possibility to predefine process variations and trace their effects on subsequent process steps and on devices and circuits fabricated, just by changing the corresponding input data. This important requirement for and capability of simulation is among others highlighted in the International Technology Roadmap for Semiconductors ITRS.
In view of this in the FP7 project SUPERTHEME a software system has been developed which enables the simultaneous assessment of the impact of systematic variations caused by process equipment and statistical variations caused by the granularity of matter on advanced More Moore and More than Moore devices and circuits. Within this workshop variability challenges will be outlined, and a selection of results obtained in SUPERTHEME will be presented. Furthermore, it is planned to also introduce related projects which are complementary to SUPERTHEME.
8:45 Welcome and Orientation
Jürgen Lorenz, Fraunhofer IISB
9:00 Variability at all Levels - A Challenge for the Semiconductor Industry
Andre Juge, ST
9:30 Overview of the SUPERTHEME Project
Jürgen Lorenz, Fraunhofer IISB
10:00 Defects Responsible for BTI in CMOS Devices: MORDRED Perspective
Alexander Shluger, UCL
10:30 Variability Aware Process Simulation in SUPERTHEME
Eberhard Bär, Fraunhofer IISB
11:00 Coffee Break
11:30 Variability Aware Process Simulation in SUPERTHEME
Asen Asenov, GU/GSS
12:00 Hierarchical Modeling of Reliability and Time Dependent Variability
in the MORV Project
Ben Kaczer, IMEC
14:00 Covering Variability from Unit Process up to Circuit Level for Mixed –
Rainer Minixhofer, ams
14:30 Variability Aware SPICE Modeling and Circuit
Simulation in SUPERTHEME
Campbell Millar, GSS
15:00 Open Discussion and Concluding Remarks
15:30 End of Workshop
Workshop 4 (Room 4, Inffeldgasse 25d, 14:00 to 17:30)
"Electromagnetic Compatibility of Integrated Circuits" (Half day)
Lead Presenter: Prof. Bernd Deutschmann, Ass.-Prof. Gunter Winkler, Graz University of Technology
Today very complex electronic systems often consisting of large digital cores, analog and mixed-signal circuits, as well as power electronic devices can be realized in one single chip. But, as device dimensions are shrinking, ICs are often becoming more susceptible to electromagnetic interferences; on the other hand internal switching frequencies of modern ICs increasing, resulting in higher electromagnetic emission. Therefore, the design of ICs that are compliant to electromagnetic compatibility (EMC) specifications has become more and more challenging during the last years. Noise signals such as radio-frequency interferences or transient disturbances such as electrostatic discharges (ESD) can interfere with the operation of the ICs and particularly with the analog circuits embedded in such devices. The undisturbed operation of electronic systems is of vital importance for safety and reliability and should therefore be of particular concern for designers of integrated circuits. In the first part of this workshop an introduction to EMC at the IC level as well as an overview of the most important EMC measurement techniques that are used for the characterization of the emission and immunity of ICs are given. In the further parts carefully selected IC design related topics such as the susceptibility to electromagnetic interferences of sensor signal conditioning circuits, the influences of packaging, connectors, PCB traces and ground planes on the performance of ICs with respect to EMC, as well as on-chip decoupling to improve the EMC of ICs will be presented.
Presentations at the conference
14:00 Introduction to EMC at the IC Level, EMC Measurement
Techniques of ICs
Bernd Deutschmann, Gunter Winkler
14:40 Susceptibility to EMI of Sensor Signal
16:00 Coffee Break
16:30 Pro and Cons of Onchip Decoupling to improve the
EMC of Integrated Circuit
17:30 End of Workshop
Workshop 5 /Room 4, Inffeldgasse 25d, 8:30 to 13:00)
"Variation-Aware Design for RF Engineers" (Half day)
Lead Presenter: Dr.-Ing. Stephan Weber, Cadence Design Systems
Creating an RF design is always a challenge, but producing it with acceptable yield is even more difficult. We start with discussing Monte-Carlo and PVT corner analysis, and their measures and problems like confidence intervals, uncertainties from non-normal distributions, etc. Then moving over to advanced techniques for yield prediction and optimization. A demo will be given using Cadence Virtuoso ADE GXL for design of RF key blocks.
Hans Meyvaert (KU Leuven, Belgium):
Switched Capacitor DC-DC Converters: Concepts and Control Techniques
Vadim Ivanov (TI, USA):
How to avoid most common mistakes in DCDC design:
--- Break ---
Luca Corradini (University of Padova, Italy):
Digital Control for Inductor Based DC-DC Converters
Jesus A. Oliver (UPM Madrid, Spain):
Ripple-Based Control Techniques for Buck Type DC-DC Converters
Workshop 6 (Room 3, Inffeldgasse 25d, 8:45 to 12:30)
"RFID Technologies Exploiting 2D and 3D Printing and Packaging Techniques" (Half day)
Lead Presenter: Prof. Wolfgang Bösch, Graz University of Technology
Radio frequency identification (RFID) is a technology that offers the possibility of reading or changing data through radio waves without the need for contact. This allows the automatic identification and location of objects and makes the collection of data easier and covers a diverse application ranges. Styrian RFID companies – mostly situated around Graz – are highly renowned in the field of RFID technologies: more than 50% of RFID chips in use worldwide have been developed in Styria. In future developments, RFID transponder (tag) realizations will exploit the capabilities of 2D and 3D printing and packaging technologies such as the inkjet printing and embedded wafer-level ball grid array (eWLB) packaging technologies. This workshop will cope with this development and will give the workshop participants insight into recent developments in these areas.
08:45 Welcome and Presentation of the RFID Hotspot in Graz/Styria
Wolfgang Boesch, Graz University of Technology
09:20 Presentation and Discussion “RFID Techno-logies Exploiting 2D
and 3D Printing and Packaging Techniques”
Jasmin Grosinger, Graz University of Technology
10:10 Presentation and Discussion “Printed Electronics – Materials,
Processes and Innovative Applications”
Andreas Klug, NanoTec Center
11:00 Coffee break
11:30 Presentation and Discussion “Advances in Packaging for
Klaus Pressel, Infineon Technologies
12:20 Final Discussion
12:30 End of Workshop
Workshop 7 (Room 6, Inffeldgasse 12, 8:30 to 13:00)
"DC-DC Converter Techniques" (Half day)
Lead Presenter: DI Christoph Sandner
This workshop will give insights into different key aspects of DC-DC converter concept and design. The designated speakers are worldwide recognized experts in this field. We target one speech in each of these fields: Inductor based converters, switched capacitor converter concepts and control techniques, buck converter control and stability, and last not least a talk about how to avoid most common mistakes in DC-DC converter circuit design.
8:30 Switched Capacitor DC-DC Converters: Concepts and Control
Hans Meyvaert, KU Leuven, Belgium
9:30 Inductor Based DC-DC Converters
10:30 Coffee Break
11:00 Ripple-Based Control Techniques for Buck Type DC-DC Converters
Jesus A. Oliver, UPM Madrid, Spain
12:00 How to Avoid Most Common Mistakes in DCDC Design: Voltage Mode,
PWM and fixed Frequency
Vadim Ivanov, TI, USA
13:00 End of Workshop
Workshop 8 (Room 3, Inffeldgasse 25d, 14:00 to 17:30)
"From Atom to Transistor"
Models and Techniques for Predictive Simulation of Emerging Devices (Half Day)
Organizer: Zlatan Stanojević, Global TCAD Solutions (Austria), firstname.lastname@example.org
Culminating in a live demonstration, this workshop discusses latest models and techniques for achieving new levels of detail in semiconductor device simulation. The used simulation tools provide excellent accordance with measured data as well as unprecedented insight in underlying physical phenomena.
50 years after the inception of Moore's Law, industry is facing ever increasing hurdles on the roadmap to produce devices which perform better and consume less power. The challenges in introduction of new technology nodes pose great risks to manufacturers, and there is always more than one possible way to proceed. Selecting apt models and tools is becoming increasingly important to efficiently gain profound data for making good decisions in device design and optimization. Especially for new technologies and nano-scaled devices, additional physical phenomena, such as quantum effects, need to be considered for meaningful analysis.
In this workshop, a methodological hierarchy of tools will be presented – ranging from atomistic models up to extraction of device parameters and optional circuit simulation, which consistently yields results well-founded in physics. Emerging device concepts will be covered, demonstrating how the chosen approach can help assess the risks involved in the introduction of new technologies. Depending on the audience’s priorities, a mixed-mode device and circuit simulation can be carried out with the generated data at the end of the live demonstration.
14:00 Extracting Materials Properties for Semiconductor Device Simulation
from Ab-Initio and Atomistic Simulation
Erich Wimmer, Materials Design s.a.r.l. (France)
14:30 Blessing or Curse: Dissipative Quantum Transport in Nano-Scale
Hans Kosina, Vienna University of Technology, Institute for Microelectronics
15:00 Just enough Quantum – Combining Semi-classical and
Quantummechanical Models for Fast and Predictive Device Simulation
Zlatan Stanojević, Global TCAD Solutions GmbH
15:30 Modeling Reliability under Variability in Nano-Scale Devices
Ben Kaczer, IMEC (Belgium)
16:00 Coffee Break
16:30 Predictive Simulation in Action: Selected Case Studies —
Zlatan Stanojević, Erich Wimmer
17:30 End of Workshop
Information for workshop organizers
ESSDERC/ESSCIRC workshops offer network of researchers a unique opportunity to exploit the logistics of the conference and the presence on-site of a large number of potential participants to meet and present the result of a project, discuss the frontiers of novel research topics, foster new collaborations, share views and know-how. Here follows a list of the fundamental information for perspective workshop organizers:
- Prospective organizers should contact the workshop program chairs Mario Auer (email@example.com), Gernot Hueber (firstname.lastname@example.org) or Bernd Deutschmann (email@example.com) by the deadlines given below with the following information:
- 24 March, 2015: title and short description of the workshop; name, affiliation and e-mail contact of the organizer(s).
- 21 April, 2015: full program of the workshop (abstract, schedule with title, time, speaker name and affiliation of each talk). The program will be posted on a dedicated page of the conference website. Alternatively, the organizers may report the URL of the website with the workshop full program. The available time-slots will be assigned on a first-come first-serve basis.
- An registration fee of € 35,00 is due by the attendees as partial coverage of the catering expenses, if they are registered participants of the main conference. Otherwise a workshop registration fee of € 120,00 is applied.
- The organizer of a workshop may also conclude a lump sum agreement with the conference organization in order to waive the individual participant’s fees.
- A room with projection equipment will be reserved for each workshop, and a lunch and two coffee breaks will be served to the attendees.
- In order not to interfere with the technical program of the conference, the workshop day is Friday, 18 September, 2015.
Prospective organizers may also be interested in taking a look at the workshop program of the last conference:
- ESSDERC/ESSCIRC 2014 workshop program (http://www.esscirc2014.org/en/sistemacongressi/european-solid-state-circuits-conference-2014/website/home/workshops/)